The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more embedded memory array blocks. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
The process of determining the hardware configuration of a device that implements a user-specified design is referred to as compilation. Typical compilation processes begin with an extraction phase, followed by a logic synthesis and technology mapping phase, a clustering and placement phase, a routing phase, and an assembly phase. The logic synthesis phase converts a user design, typically expressed in terms of a register transfer level description, into a corresponding set of registers, logic gates, and other circuit components. For programmable device, a technology mapping phase, which is often considered part of logic synthesis, permutes the set of registers, logic gates, and other circuit components over the hardware architecture of a programmable device in order to match elements of the user design with corresponding portions of the programmable device.
A logic synthesis phase often converts a user design into many different equivalent sets of logic gates to determine an optimal set of logic gates implementing the user design. Logic synthesis may optimize the set of logic gates to meet different performance criteria, such as minimizing the area or device resources required, maximizing the operating speed of the design, or minimizing the power consumption of the design.
Timing-driven synthesis is one logic synthesis approach that utilizes timing information about the user design to determine a timing-optimal set of logic gates implementing the user design. In timing-driven synthesis, the timing information indicates which portions of the design are timing critical. The logic synthesis phase uses this timing information to create timing-optimized subsets of logic gates corresponding with the timing-critical portions of the user design, while optimizing logic gates corresponding with the non-timing-critical portions of the design for other performance criteria.
Unfortunately, it is often difficult to determine accurate timing information for a user design prior to the synthesis phase. The precise timing characteristics of a design are unknown until after the logic synthesis and subsequent compilation phases are complete. Timing estimation techniques may be used to estimate the timing characteristics of a design based on a given set of logic gates determined during the logic synthesis phase. However, the subsequent placement and routing phases of compilation greatly influence the final timing characteristics of the design. Therefore, timing estimation techniques based on the set of logic gates specified during logic synthesis are often very inaccurate. As a result, timing-driven synthesis often does not optimize designs as well as expected due to inaccurate timing information.
It is therefore desirable for a system and method to provide improved timing information for logic synthesis and technology mapping. It is also desirable for logic synthesis and technology mapping phases to provide improved optimization and require less compilation time by utilizing the improved timing information.